1. Field of the Invention
Embodiments of the present invention relate generally to power management and more specifically to a method and system for implementing generalized system stutter.
2. Description of the Related Art
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Energy efficiency is becoming an increasingly important consideration in many system designs. Memory manufacturers have developed memory systems with multiple power states, such as active, active idle, power-down, and self-refresh. A memory system typically needs to be in the active state to service a request, and the remaining power states are in order of decreasing power consumption but increasing time to transition back to active. In other words, the active state consumes the most power, and the self-refresh state incurs the most delay for clock resynchronization. Similarly, system interconnect links are also associated with multiple power states, with the lowest power state again corresponding to the highest latency. Thus, one approach of achieving energy efficiency is to maintain a memory system, a system interconnect link, or both in the lowest power state for as long as possible, while effectively managing the high latencies associated with entering and exiting such a state.
To illustrate, suppose a display system 110 is the only active agent in a computing device 100 during a low power state, in which system memory 106 is in the self-refresh state, and a system link 108 is in the power-down state. FIG. 1A is a simplified block diagram of a computing device 100 capable of displaying data in this low power state. The display system 110 of the computing device 100 includes a display engine 112, a display device 114, and a display first-in-first-out (“FIFO”) buffer 116. The display engine 112 utilizes the display FIFO buffer 116 to decouple the stringent timing requirements of the display device 114 from the memory system 106. So, to be able to survive potentially significant latency associated with “waking up” the system memory 106 from the low power state just to retrieve data, the display engine 112 ensures that the display FIFO buffer 116 stores sufficient pixel data to satisfy the timing requirements of the display device 114 during the low power state. Specifically, while the computing device 100 resides in the low power state, the display engine 110 processes and drains the data in the display FIFO buffer 116 in a direction 118. When the display engine 110 hits a pre-determined critical watermark in the display FIFO buffer 116, the display engine 110 initiates the process of exiting the low power state and fetching data from the system memory 106 to fill up the display FIFO buffer 116 in a direction 120. This filling up process is also referred to as “topping off” the display FIFO buffer 116.
FIG. 1B is a timing diagram illustrating one pattern of system memory accesses by a display system without a display FIFO buffer to optimize power efficiency and a display engine, whereas FIG. 1C is a timing diagram illustrating a different pattern of system memory accesses by the display system 110 with the display FIFO buffer 116 to optimize power efficiency and the display engine 112. Without the power efficiency optimization, the gap between any two memory accesses, denoted as access gap 150, is typically less than the latency associated with entering or exiting a low power state, such as the self-refresh state. On the other hand, with an appropriated sized display FIFO buffer 116, the memory accesses can be clustered, and an access gap 160 can be lengthened to be at least equal to the latency associated with entering or exiting the self-refresh state. This clustering of memory access requests and lengthening of access gaps are collectively referred to as “display stutter.” With the pattern shown in FIG. 1C, the computing device 100 is able to achieve the desired energy efficiency.
However, in addition to the display system 110, the computing device 100 has various input/output (“I/O”) agents that request to access the system memory 106 via the system link 108 and a chipset 104. Some examples of these I/O agents include, without limitation, an Integrated Driver Electronics (“IDE”) device, a Universal Serial Bus (“USB”) device, a network controller, a Peripheral Component Interconnect Express (“PCI Express”) controller, a PCI bridge, and a PCI-X controller. Each of the N I/O agents has its own distinct timing requirements, and many of the I/O agents do not support stutter requirements. Although redesigning each of the I/O agents to issue memory access requests leading to a similar memory access pattern as the one shown in FIG. 1C may improve the energy efficiency of the computing device 100, the risks and the costs of tinkering with multiple working devices, especially the legacy I/O agents that have already been widely adopted, are likely to far outweigh any such improvement.
As the foregoing illustrates, what is needed in the art is a generalized system stutter that can be easily deployed and addresses at least the shortcomings of the prior art approaches set forth above.